Publications
Published Journals
[TSUSC’23] Ke Wang, Hao Zheng, Jiajun Li, Ahmed Louri. “Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration.” in IEEE Transactions on Sustainable Computing, DOI: 10.1109/TSUSC.2023.3313880, 2023
[JCST’23] Jiajun Li, Ke Wang, Hao Zheng, Ahmed Louri. “GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators.” in Journal of Computer Science and Technology, 2023
[TCAS-I’22] Yuan Li, Ke Wang, Hao Zheng, and Ahmed Louri. “ASCEND: A Scalable and Energy-Efficient DNN Accelerator with Photonic Interconnects.” in IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), pp. 1-13, doi: 10.1109/TCSI.2022.3169953, April, 2022
[TSUSC’21] Ke Wang, Hao Zheng, Yuan Li, Ahmed Louri. “SecureNoC: A Learning-enabled, High-performance, Energy-efficient, and Secure On-chip Communication Framework Design.” in IEEE Transactions on Sustainable Computing, pp. 1-15, DOI: 10.1109/TSUSC/2021.3138279, December, 2021
[TPDS’21] Jiajun Li, Hao Zheng, Ke Wang, Ahmed Louri. “SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator with Workload Balancing.” in IEEE Transactions on Parallel and Distributed Systems: Special Section on Parallel and Distributed Computing Techniques for AI, ML, and DL, 2021
[IEEE MICRO’20] Ke Wang, Hao Zheng, Ahmed Louri. “TSA: Learning-Based Threat Detection and Mitigation for Secure System-On-Chip Architectures.” IEEE Micro: Special Issue on Machine Learning for Systems, Sept/Oct, 2020
[TPDS’20] Ke Wang and Ahmed Louri. “CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning.” IEEE Transactions on Parallel and Distributed Systems 31.9 (2020),pp. 2125–2138., 2020
Conference
Proceedings
[ISCA’23] Jiajun Li, Yuxuan Zhang, Hao Zheng, Ke Wang. “FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations.” Proceedings of the 50th Annual International Symposium on Computer Architecture, Orlando, FL, USA, June 17-18, 2023.
[ICCD’22] Yingnan Zhao, Ke Wang, and Ahmed Louri. “FSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator Architecture.” accepted to appear in Proceedings of The 40th IEEE International Conference on Computer Design, Lake Tahoe, USA, October 23-26, 2022.
[DATE’22] Ke Wang, Hao Zheng, Yuan Li, Jiajun Li, and Ahmed Louri. “AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems.” in Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium,March 14-15, 2022
[HPCA’21] Hao Zheng, Ke Wang, Ahmed Louri. “Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures.” in Proceedings of the 27th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Feb 27 - Mar 3, 2021.
[DAC’21] Hao Zheng, Ke Wang, Ahmed Louri. “A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures.” in Proceedings of the 57th Design Automation Conference (DAC), July19-23, 2020 (Best Paper Award Nominee)
[ISCA’19] Ke Wang, Avinash Karanth, Razvan Bunescu, and Ahmed Louri. “IntelliNoC: a holistic design framework for energy-efficient and reliable on-chip communication for manycores.” in Proceedings of the 46th International Symposium on Computer Architecture (ISCA). Phoenix, AZ, June, 2019
[DATE’19] Ke Wang, Avinash Karanth, Razvan Bunescu, and Ahmed Louri. “High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learning.” in Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE). Florence, Italy, 2019 (Best Paper Award Nominee)
Patents
Hao Zheng, Ke Wang, and Ahmed Louri. “Interconnection Network with Adaptable Router Lines for Chiplet-based Manycore Architecture.” U.S. Patent, No. 11,489,788, Granted on November 1, 2022.
Ke Wang, Hao Zheng, and Ahmed Louri. “Learning-Based High-Performance, Energy-Efficient, and Secure Interconnection Design Framework.” U.S.Patent No. 17/307, 563, Filed May 4, 2021
Ke Wang and Ahmed Louri. “Learning-Based High-Performance, Energy-Efficient, Fault-Tolerant On-Chip Communication Design Framework.” U.S.Patent No. 16/547, 297, Filed August 21, 2019.