Technology scaling down to the nanometer regime has aided the growth in transistors that have made multi-core parallel computing architectures a power-efficient approach to harness parallelism and improve performance. The proliferation of multiple cores on the chip has signaled the advent of communication-centric, rather than computation-centric systems. Consequently, many multicore designs have adopted Network-on-Chip (NoC) as the communication fabric. A NoC can be abstracted into three layers, namely a physical/circuit layer, a data/message layer, and a network layer. However, as technology scales, NoCs are facing serious challenges including scaling performance, minimizing power consumption, providing a reliable communication infrastructure that can tolerate faults, and protecting data from security vulnerabilities. While research that tackles these challenges is beginning to emerge, most current solutions concentrate on a single NoC layer and fail to address all the challenges mentioned above simultaneously. These solutions tend to possess limited knowledge of the overall system and are therefore reactive in behavior, making worst-case assumptions and over-provisioning, and as a result, they introduce significant overheads in terms of power, area, and performance. It is becoming evident that piecemeal solutions that address an individual power problem, failure mode, attack model, or a performance deficiency within a single NoC layer will increasingly be harder to deploy in future multi-core architectures, could potentially conflict with each other, and could completely miss significant opportunities for overall design optimization due to dynamic cross-layer interactions and complex design trade-offs.

 

Dr. Wang and his research team tackles the critical NoC design challenges by developing an intelligent, adaptive, multi-layer approach design framework for multicore systems. The overarching goal is to enable cooperation and dynamic adaptation across all system abstraction layers to obtain globally-optimal solutions for system-level reliability, performance, power, security, and cost. Besides the development of NoC enhancement techniques with hardware innovations, machine-learning-based control mechanisms will be designed to accurately capture dynamic cross-layer interactions and auto-tune NoC functionality for improved system-level performance metrics. The principal thrusts of the project span various system layers from dynamic modeling of complex cross-layer interactions, flexible interconnect microarchitecture design, NoC security vulnerability exploration and countermeasure development, to machine learning algorithms and applications and proof-of-concept implementation. This project will significantly advance the fundamental understanding of the interplay between the NoC and the rest of the components on the chip (cores, memory, etc.) as well as design tradeoffs between performance, power, reliability, security, and cost in current and future parallel computing systems.